The present invention is directed to semiconductor memories and, more particularly, to a single port memory that emulates a dual port memory.
Dual-port memory is widely used since single-cycle dual-port mode of operation allows read and write operations to be performed simultaneously, or nearly simultaneously, whereas single-port random-access memory (RAM) only allows one access at a time. This confers some performance advantages on dual-port memory as compared to single-port memory. However, dual-port memory may be excluded from some designs because it is less reliable at low voltages and more sensitive to low voltage failures. For example, because they are less reliable, dual-port memories are excluded from most circuits used in automotive and medical applications. On the other hand, the circuits used for automotive applications are otherwise much the same as those used in applications with less stringent safety and reliability requirements. Therefore, there is a need to operate single-port memories as if they were dual-port memories so that the other common circuitry may be shared.
It is possible for a single-port memory to operate in a dual-port mode. This can be achieved by accessing the single-port memory in alternate clock cycles, or at alternate edges of the clock cycles. However, this approach effectively limits the dual-port mode of operation to half the maximum clock frequency of a dual port memory.
A single-port memory that operates in single-cycle dual-port mode can avoid such a halving of maximum clock frequency by providing two single-port memory banks, duplicating the memory capacity of the equivalent dual-port memory, and with a register to discriminate the read/write addresses. However, this approach is expensive in terms of circuit area.
Accordingly, there is a need for a single-port memory that can operate in a dual-port mode but that does not compromise system performance.